
IBM has announced what it describes as a historic milestone in semiconductor engineering: the development of the world's first known chip technology built at a scale smaller than 1 nanometre. The company calls the design a block-of-flats architecture — a three-dimensional approach to packing transistors that breaks through what many engineers had considered a fundamental physical barrier.
For decades, the semiconductor industry has advanced by making transistors smaller — shrinking them from micrometres to nanometres — allowing more computing power to be packed into the same physical space. The current state of the art in commercial chip production sits at around 2 nanometres. IBM's sub-1nm work pushes beyond that threshold into territory that physicists had flagged as deeply challenging due to quantum effects at such tiny scales.
IBM's engineers used a stacking design — likened to building upward like a block of flats rather than spreading outward — to achieve the density needed for sub-nanometre transistor placement. This three-dimensional approach has been gaining traction across the industry as a way to continue improving performance without hitting the limits of two-dimensional miniaturisation.
IBM was careful to note that the technology remains in a research phase and will not be production-ready for some time. Bringing a new chip architecture from the lab to mass manufacturing involves years of engineering work, yield optimisation and massive capital investment. However, announcements of this type typically signal that a technology will reach commercial maturity within a decade.
The announcement comes as the United States and its allies have been aggressively investing in domestic semiconductor capacity and restricting exports of advanced chip technology to China. A demonstrated capability to move below 1nm reinforces the West's technological edge in chip design at a moment of intense geopolitical competition over semiconductor supremacy.
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